// 存储器

module Mem (
    input clk,W,R,
    input [15:0] DI,A,
    output wire [15:0] DO,
    input [15:0] PC,
    output wire [15:0] Inst
);

    reg [15:0] register [31:0];
    reg W_delay1,W_delay2;

    assign Inst = register[PC[4:0]];
    integer i;

    initial begin
        $readmemb("E:/CODE/Verilog HDL/verilog_course/CPU/src/SUM.dat",register);
    end

    assign DO = (R)? register[A]:0;

    // always @(posedge clk) begin
        
    // end

    always @(posedge clk) begin
        if (W == 1'b1) begin
            register[A] <= DI;
        end
    end



endmodule